library IEEE;
Library UNISIM;
use IEEE.STD_LOGIC_1164.ALL;
use UNISIM.vcomponents.all;

entity multiplier_16x16 is
	PORT (
		op1 : in STD_LOGIC_VECTOR(15 downto 0);
		op2 : in STD_LOGIC_VECTOR(15 downto 0);
		res : out STD_LOGIC_VECTOR(31 downto 0)
	);

end multiplier_16x16;

architecture Behavioral of multiplier_16x16 is
	component MULT18X18
	port (
		P : out STD_LOGIC_VECTOR (35 downto 0);
		A : in STD_LOGIC_VECTOR (17 downto 0);
		B : in STD_LOGIC_VECTOR (17 downto 0));
	end component;
	
	signal internal_zeros : STD_LOGIC_VECTOR(3 downto 0);
begin

	MULT18X18_INSTANCE_NAME : MULT18X18	
	port map (
		P(31 downto 0) => res,
		P(35 downto 32) => internal_zeros,
		A(15 downto 0) => op1,
		A(17 downto 16) => "00",
		B(15 downto 0) => op2,
		B(17 downto 16) => "00"
	);

end Behavioral;
